This invention relates to semiconductor memories, and more particularly to binary random access memories (RAM) having an array of improved memory cells.
During the past several years, much time, effort, and money has gone into the development of high density, low cost memories. This is because the computer industry has continually demanded more and more storage capacity. As a result of this past memory development work, the number of bits of storage per chip has increased from 16 to 16,000. In addition, the cost per bit has been decreased by a factor of approximately 200.
A major reason for this progress has been the development of small, reliable memory cells. Thousands of these cells are formed on a single chip; and the chips are interconnected to form larger memories. The cost in the production of semiconductor chips is such that most of the expense is in bonding, packaging, testing, handling, and the like, rather than in the cost of the small chip of silicon which contains the actual circuitry. Thus, any circuit which can be contained within a chip of a given size, for example, 30,000 square mils, will cost about the same as any other. By forming large numbers of memory cells in a chip, large economies in the cost per bit can result if reasonable yields are obtained. However, as the size of a chip increases, the yield decreases; so that the advantages of larger chip sizes are outweighed by reduction in yields. Presently, chips of about 150-250 mils on a side are commonly made in the semiconductor industry. Accordingly, it is desirable to reduce the area occupied by each cell.
Three types of cells are currently used in the construction of semiconductor memory chips. These memory cell types are called the one transistor cell (1-T cell), the double level polysilicon cell (DLP cell), and the charge coupled cell (CC cell). The two former cell types are described in U.S. Pat. Nos. 3,387,286 by R. H. Dennard and 3,720,922 by W. F. Kosonocky, respectively. The CC RAM cell is described in copending application Ser. No. 354,889 filed Mar. 3, 1975 by A. Tasch, Jr. et al, abandoned in favor of continuation application Ser. No. 739,758 filed Nov. 8, 1976, now U.S. Pat. No. 4,060,738 issued Nov. 29, 1977.
As alluded to earlier, the 1-T cell, the DLP cell, and the CC cell each is the product of many years of work and refinement. Thus, it could be expected that large improvements in such a developed field are unlikely. However, the present invention includes a novel cell - termed a "high capacity" or "hi-C" cell - which has several significant advantages over the prior art.
One important limitation of the 1-T, DLP, and CC cells is that they all have less charge capacity per unit area than is desirable. A high charge capacity per unit area is desired because as the number of bits per chip increases, the size of each cell must necessarily decrease. Thus the amount of charge that can be stored in each cell decreases. And eventually, a point is reached beyond which the cell cannot be reduced further because the amount of charge that the cell can store is indistinguishable from noise. Thus, charge capacity per unit area is a fundamental limitation on the minimum cell size.
The 1-T and DLP cells are also deficient in a second parameter - which is called leakage current. The leakage current is a measure of the quantity of electron-hole pairs that are thermally generated in a cell. These charge carriers are undesirable because they alter the amount of charge that is stored as information, and eventually they totally cancel the information charge. In order to avoid this cancelling effect, the information charge in the cell must be periodically refreshed at certain minimum intervals. The refresh period is inversely proportional to the leakage current in the cell. It is an experimentally verified fact that leakage current in the 1-T and DLP cells is typically 3 to 8 times greater than that of the CC cell. But on the other hand, charge capacity of the CC cell is only approximately half the charge capacity of the 1-T or DLP cells. Thus, no single cell type has the best of both parameters.
Because of these and other limitations in the prior art, and because of the demand for more bits of storage per chip, it is therefore one object of this invention to provide a process for constructing an array of improved memory cells.
It is another object of the invention to provide a process for constructing a memory cell having an increased storage capacity per unit area.
It is still another object of the invention to provide a process for constructing a memory cell having low leakage current while at the same time having increased storage capacity per unit area.